Job Title: Design Verification Engineer
Location: Mountainview CA (Onsite)
Experience Level: 5+ years (Relevant)
Note: We are seeking a Design Verification Engineer with strong SV, UVM and AXI experince.
Strong expertise along-with complex SoC/IP debug is must
At-least 5+ years of experience in System Verilog HVL and C/C++.
AMBA AXI bus along-with ARM or C based processor
Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.
Low Power Verification in UPF/net-list Simulation good to have
Make/Perl/Python
Ensure customer satisfaction.
Reporting to customer on daily or weekly progress effectively
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